JM
Julien Michel
FPGA Engineer - ASIC Design Team chez College of Engineering and Architecture of Fribourg
Bassecourt, Jura, SwitzerlandCoordonnées
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Activité professionnelle
PosteFPGA Engineer - ASIC Design Team
EntrepriseCollege of Engineering and Architecture of Fribourg
Domaineheia-fr.ch
LocalisationBassecourt, Jura, Switzerland